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ics for communications memory time switch extended large mtsxl peb 2447 version 1.2 data sheet 03.97 t2447-xv12-d2-7600
edition 03.97 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. peb 2447 revision history: current version: 03.97 (editorial update) previous version: 01.95 page (in previous version) page (in current version) subjects (major changes since last revision) - 32 register address arrangement (new)
peb 2447 table of contents page semiconductor group 3 03.97 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 general device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.5 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2.1 control memory reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2.2 evaluate frame measurement signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2.3 mtsxl selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3 boundary scan and tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3.1 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3.2 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.3.3 use of built in selftest via the boundary scan interface . . . . . . . . . . . . . . . .19 2.3.4 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.1 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.2 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.3 indirect access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.4 frame evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.5 input offset and output offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.6 frame delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.1 register address arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.2 mode register (modr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.3 command register (cmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.4 status register (star) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.5 interrupt status register (ista) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.6 mask register (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.7 memory access address/code register high (mach) . . . . . . . . . . . . . . . . .37 4.8 memory access address register low (maal) . . . . . . . . . . . . . . . . . . . . . .38 4.9 memory read data register low (mrdl) . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.10 memory read data register high (mrdh) . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.11 memory write data register low (mwdl) . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.12 memory write data register high (mwdh) . . . . . . . . . . . . . . . . . . . . . . . . .40 4.13 input clock shift register bank icsr (15:0) . . . . . . . . . . . . . . . . . . . . . . . . .41 4.14 output clock shift register (oscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.15 test register (tstr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.16 frame evaluation register low (ferl) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.17 frame evaluation register high (ferh) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
p-mqfp-100-2 semiconductor group 4 03.97 memory time switch extended large mtsxl peb 2447 version 1.2 cmos ic type ordering code package peb 2447 h q67103-h6594 p-mqfp-100-2 1overview 1.1 features ? non blocking time/space switch for 4.096- or 8.192-mbit/s pcm systems ? device clock 16.384 mhz ? switching of up to 2048 incoming pcm channels to up to 2048 outgoing pcm channels ? 32 input and 32 output pcm lines ? tristate function for further expansion and tandem operation ? m p read access to pcm data ? programmable clock shift with half clock step resolution for input and output ? individual line delay measurement for 6 additional inputs ? individual input offset programmable for 16 pcm inputs ? boundary scan (fully ieee1149.1 compatible) ? built-in selftest (also usable via boundary scan interface) ? 8-bit intel type demultiplexed m p interface ? all registers accessible by direct addressing ? in-operation adjustment of bit sampling without bit errors ? low power consumption ? single 5 v power supply
peb 2447 overview semiconductor group 5 03.97 1.2 logic symbol figure 1 functional symbol 1.3 general device overview the siemens memory time switch extended large mtsxl (peb 2447) is a capacity expansion of the mtsl (peb 2047). it is a monolithic cmos switching device capable of connecting maximally 2048 pcm input time slots to 2048 output time slots. in order to manage the problem of different line delays, six additional fs inputs can be used as frame measurement inputs and 16 different input offsets of pcm frames are allowed. thus a frame wander can be compensated by adjusting the input offset during operation. a special circuitry guarantees that no bit error will occur, when reprogramming the input offsets. the mtsxl on chip connection memory and data memory are accessed via the 8-bit standard m p interface (intel demultiplexed type). a built-in selftest mechanism C also activated by the m p C ensures proper device operation in the system. the peb 2447 is fabricated using the advanced cmos technology from siemens and is mounted in a p-mqfp-100-2 package. inputs and outputs are ttl compatible.
peb 2447 overview semiconductor group 6 03.97 1.4 pin configuration (top view) figure 2 1.5 pin definitions and functions pin no. symbol input (i) output (o) tristate (t) function 14 41 67 v ss i ground (0 v) 13 40 66 v dd i supply voltage: 5 v + 5 %. itp09593 in20 in21 in22 in23 in24 in25 in26 in27 in28 in29 in30 in31 clk fs0 fs1 fs2 fs3 fs4 fs5 a4 a3 a2 a1 a0 cs res wr rd 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 in19 100 99 in18 98 in17 97 in16 96 in15 95 in14 94 in13 93 in12 92 in11 91 in10 90 in9 89 in8 88 in7 87 in6 86 in5 85 in4 84 in3 83 in2 82 in1 81 in0 sp 31 d7 32 d6 33 d5 34 d4 35 d3 36 d2 37 d1 38 d0 39 40 41 out31 42 out30 43 out29 44 out28 45 out27 46 out26 47 out25 48 out24 49 out22 50 out21 out20 out19 out18 out17 out16 out15 out14 out13 out12 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0 int tdo tms tdi tck out23 dd v v ss v dd v ss index marking ss v v dd peb 2447
peb 2447 overview semiconductor group 7 03.97 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 in16 in17 in18 in19 in20 in21 in22 in23 in24 in25 in26 in27 in28 in29 in30 in31 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i pcm input ports: serial data is received at standard ttl levels. 15 clk i clock: 16.384 mhz device clock. 1.5 pin definitions and functions (contd) pin no. symbol input (i) output (o) tristate (t) function
peb 2447 overview semiconductor group 8 03.97 16 17 18 19 20 21 fs0 fs1 fs2 fs3 fs4 fs5 i i i i i i frame measuring inputs: these inputs are used as frame evaluation inputs. 26 25 24 23 22 a0 a1 a2 a3 a4 i i i i i address bus bit 0 to 4: these inputs interface to the systems address bus to select an internal register for a read or write access. 27 cs i chip select: (low active) a low level selects the mtsxl for a register access operation. 28 res i reset: a high signal on this input forces the mtsxl into reset state. 29 wr i write: (low active) this signal indicates a write operation. 30 rd i read: (low active) this signal indicates a read operation. 31 sp i synchronization pulse: the mtsxl is synchronized to the pcm system via this line. 39 38 37 36 35 34 33 32 d0 d1 d2 d3 d4 d5 d6 d7 i/o/t i/o/t i/o/t i/o/t i/o/t i/o/t i/o/t i/o/t data bus: these pins transfer data between the m p and the mtsxl. 1.5 pin definitions and functions (contd) pin no. symbol input (i) output (o) tristate (t) function
peb 2447 overview semiconductor group 9 03.97 75 74 73 72 71 70 69 68 out0 out1 out2 out3 out4 out5 out6 out7 o/t o/t o/t o/t o/t o/t o/t o/t pcm output port: serial data is sent by these lines. these pins can be tristated. 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 out8 out9 out10 out11 out12 out13 out14 out15 out16 out17 out18 out19 out20 out21 out22 out23 out24 out25 out26 out27 out28 out29 out30 out31 o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t o/t 76 int o (open drain) interrupt line: active low. reset when reading ista 77 tdo o/t test data output: in the appropriate tap controller state test data, an instruction or the selftest result is shifted out via this line. 1.5 pin definitions and functions (contd) pin no. symbol input (i) output (o) tristate (t) function
peb 2447 overview semiconductor group 10 03.97 78 tms i (internal pull-up) test mode select: 0 -> 1 transitions on this pin are required to step through the tap controller state machine. 79 tdi i (internal pull-up) test data input: in the appropriate tap controller state test data or an instruction is shifted in via this line. 80 tck i test clock: single rate test data clock (6.25 mhz) 1.5 pin definitions and functions (contd) pin no. symbol input (i) output (o) tristate (t) function
peb 2447 functional description semiconductor group 11 03.97 2 functional description the mtsxl is a memory time switch device. operating with a device clock of 16.384 mhz it can connect any of 2048 pcm input channels to any of 2048 output channels. a general block diagram of the mtsxl is shown in figure 3 . 2.1 general operation the input information of a complete frame is stored twice in the two on-chip 16-kbit data memories dm 0 and dm 1 (data memory 0 and data memory 1). the incoming 2048 channels of 8 bits each are written in sequence into fixed positions of dm 0 and dm 1. this is controlled by the input counter in the timing control block with a 8 khz repetition rate. for outputting, two connection memories (cm 0 and cm 1) are read in sequence synchronously. each entry in the connection memory cm 0 / cm 1 points to a location in data memory dm 0 / dm 1. the byte in this data memory location is transferred into the current output time slot. the read access to the cms is controlled by an output counter. cm 0 supplies the pcm data for outputs out0 to out15, cm 1 supplies the pcm data for outputs out16 to out31.
peb 2447 functional description semiconductor group 12 03.97 figure 3 block diagram of mtsxl the synchronization of the input and output counters is achieved by a rising edge of the sync pulse sp, which is always sampled with the falling edge of the device clock. different modes of operation are configurable at the pcm interfaces (see table 9 ). furthermore, 16 pcm input lines can be aligned with individual clock shift values to compensate different line delays. if 32 inputs are used, one clock shift value controls two ports at the same time. shifting of the output frame is also possible, but all output lines are affected the same way. the input lines fs0 to fs5 are used as frame measurement inputs. after synchronizing the device by the sp pulse the fs inputs can be evaluated on a per port basis. this evaluation procedure is started by a microprocessor command. as a result the input counter value on the rising edge of the fs signal can be read from an internal register. thus delay compensation is easily managed by programming appropriate clock shift values and/or a possible software offset.
peb 2447 functional description semiconductor group 13 03.97 during operation of the chip a frame length check is also supplied, which controls correct synchronization by the sp pulse and generates an interrupt in case of lost or achieved synchronization. the unused output ports are tristated by mode selection, whereas unused time slots are tristated by an additional bit in the control memory. by using this tristate capability the mtsxl can be easily expanded to a time switch of any size. the standard 8-bit m p interface can communicate with intel demultiplexed microprocessors. it gives access to the internal registers and to the control and data memory. all registers are directly addressable. the memories are accessed by a simple four byte indirect access method. 2.2 special functions the activity of all special functions can be read in the status register. completion of these functions is indicated by interrupts. 2.2.1 control memory reset initialization of the device after a hardware reset (res) is easily done with a m p command control memory reset. after finishing this procedure all control memory channels contain the information tristated. apart from this tristate information the contents of the c memory is undefined. 2.2.2 evaluate frame measurement signal a command including the address (0 5) will be given by the m p. the rising edge of the corresponding frame measurement signal (fs0 fs5) will be evaluated. the exact timing of the fs edge can then be read from an internal 12-bit register (resolution of a complete 8 khz frame in half 16 mhz clock periods). 2.2.3 mtsxl selftest the switching path of the mtsxl including input buffer, data memory, control memory, output buffer and timing control can be tested in the system by a 2-step built-in selftest. activating this mechanism takes 2 0.625 ms (16.384 mhz). finally the result selftest ok/selftest not ok can be read from the internal status register. after test completion the control memory has also been reset (contains the information tristated). the selftest can also be started and checked via the boundary scan interface. note: for correct execution of the built-in selftest the mtsxl needs a value of icsr = 00. if modr:psb = 0 (e.g. after hardware reset) this value is programmed automatically after start of the selftest procedure. if icsr does not contain 00 with modr:psb = 1 the selftest will fail.
peb 2447 functional description semiconductor group 14 03.97 2.3 boundary scan and tap controller 2.3.1 boundary scan the mtsxl provides fully ieee std. 1149.1 compatible boundary scan support consisting of C a complete boundary scan C a test access port controller (tap controller) C four dedicated pins (tck, tms, tdi, tdo) C a 32 bit idcode register all pins except power supply and ground are included in the boundary scan. depending on the pin functionality one, two or three boundary scan cells are provided: when the tap controller is in the appropriate mode data is shifted into / out of the boundary scan via the pins tdi / tdo using the 6.25 mhz clock on pin tck. the mtsxl pins are included in the boundary scan in the following sequence: table 1 boundary scan cell type pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable table 2 boundary scan sequence boundary scan number tdi -> pin number pin name type number of scan cells default value 181in0i10 282in1i10 383in2i11 484in3i10 585in4i10 686in5i10 787in6i10 888in7i10 989in8i10 10 90 in9 i 1 0 11 91 in10 i 1 0
peb 2447 functional description semiconductor group 15 03.97 12 92 in11 i 1 0 13 93 in12 i 1 0 14 94 in13 i 1 0 15 95 in14 i 1 1 16 96 in15 i 1 0 17 97 in16 i 1 0 18 98 in17 i 1 1 19 99 in18 i 1 0 20 100 in19 i 1 1 21 1 in20 i 1 0 22 2 in21 i 1 0 23 3 in22 i 1 0 24 4 in23 i 1 0 25 5 in24 i 1 1 26 6 in25 i 1 0 27 7 in26 i 1 0 28 8 in27 i 1 0 29 9 in28 i 1 0 30 10 in29 i 1 0 31 11 in30 i 1 1 32 12 in31 i 1 1 33 15 clk i 1 0 34 16 fs0 i 1 0 35 17 fs1 i 1 0 36 18 fs2 i 1 0 37 19 fs3 i 1 0 38 20 fs4 i 1 0 39 21 fs5 i 1 0 40 22 a4 i 1 0 41 23 a3 i 1 0 42 24 a2 i 1 0 table 2 boundary scan sequence (contd) boundary scan number tdi -> pin number pin name type number of scan cells default value
peb 2447 functional description semiconductor group 16 03.97 43 25 a1 i 1 0 44 26 a0 i 1 0 45 27 cs i1 0 46 28 res i 1 0 47 29 wr i1 0 48 30 rd i1 0 49 31 sp i 1 0 50 32 ad7 io 3 000 51 33 ad6 io 3 000 52 34 ad5 io 3 000 53 35 ad4 io 3 000 54 36 ad3 io 3 000 55 37 ad2 io 3 000 56 38 ad1 io 3 000 57 39 ad0 io 3 000 58 42 out31 o 2 00 59 43 out30 o 2 00 60 44 out29 o 2 00 61 45 out28 o 2 00 62 46 out27 o 2 00 63 47 out26 o 2 00 64 48 out25 o 2 00 65 49 out24 o 2 00 66 50 out23 o 2 00 67 51 out22 o 2 00 68 52 out21 o 2 00 69 53 out20 o 2 00 70 54 out19 o 2 00 71 55 out18 o 2 00 72 56 out17 o 2 00 73 57 out16 o 2 00 table 2 boundary scan sequence (contd) boundary scan number tdi -> pin number pin name type number of scan cells default value
peb 2447 functional description semiconductor group 17 03.97 74 58 out15 o 2 00 75 59 out14 o 2 00 76 60 out13 o 2 00 77 61 out12 o 2 00 78 62 out11 o 2 00 79 63 out10 o 2 00 80 64 out9 o 2 00 81 65 out8 o 2 00 82 68 out7 o 2 00 83 69 out6 o 2 00 84 70 out5 o 2 00 85 71 out4 o 2 00 86 72 out3 o 2 00 87 73 out2 o 2 00 88 74 out1 o 2 00 89 75 out0 o 2 00 90 76 int o2 00 table 2 boundary scan sequence (contd) boundary scan number tdi -> pin number pin name type number of scan cells default value
peb 2447 functional description semiconductor group 18 03.97 2.3.2 tap controller the tap controller implements a state machine defined in the jtag standard ieee1149.1. the instruction register of the controller is extended to 4 bits in order to increase the number of instructions. this is necessary for the use of the build in selftest procedure via the boundary scan interface: the standard instructions are implemented according to the jtag standard, just the instruction register is extended to 4 bits. at the new instructions tap_test1.. 8 special internal test signals are activated during the state run test / idle. the mtsxl only uses tap_test1 and tap_test2 according to table 3 . table 3 instruction code of 4 bit tap controller instruction code extest 0000 intest 0001 sample / preload 0010 idcode 0011 bypass 11xx tap_test1: start built in self test 0100 tap_test2: write selftest control register 0101 tap_test3 0110 tap_test4 0111 tap_test5 1000 tap_test6 1001 tap_test7 1010 tap_test8 1011
peb 2447 functional description semiconductor group 19 03.97 the extended tap controller uses a modified data path: when tap_test1 / 2 is activated the data path is set to shift the result of the selftest procedure (bit star:stok) out through the tdo pin. 2.3.3 use of built in selftest via the boundary scan interface the built in self test is used by the following steps: C the instruction tap_test2 is shifted into the tap controller (see figure 4 ) C stp command is shifted into the selftest control register (see table 5 and figure 5 ) C the instruction tap_test1 is shifted into the tap controller to start the selftest (see figure 6 ) after 10240 tck periods: C bit star:stok can be shifted out (see figure 7 ) . note: st [2:0] represent the bits cmdr:stp2..0 but do not overwrite them. table 4 data path of 4 bit tap controller instruction code input data path output 11xx tdi ? tdo 00xx bsout ? tdo 0011 bsout_id ? tdo 01xx tdi2: star:stok (internal) ? tdo 10xx tdi3: vss (not used, internal) ? tdo table 5 4 bit selftest control register bit function st [0] cmdr:stp0 st [1] cmdr:stp1 st [2] cmdr:stp2 st [3] 1 built in selftest 0 no built in selftest
peb 2447 functional description semiconductor group 20 03.97 the tap controller state machine passes through the different states according to figures 4 to 7 . note: the state coding is only described for explanation purposes, it is externally not visible. table 6 states of tap controller (explanation for figures 4 to 7 ) controller state state code exit2-dr 0 exit1-dr 1 shift-dr 2 pause-dr 3 select-ir-scan 4 update-dr 5 capture-dr 6 select-dr-scan 7 exit2-ir 8 exit1-ir 9 shift-ir a pause-ir b run-test / idle c update-ir d capture-ir e test-logic-reset f
peb 2447 functional description semiconductor group 21 03.97 figure 4 starting instruction tap_test2 (code 0101) figure 5 writing selftest control register
peb 2447 functional description semiconductor group 22 03.97 figure 6 start of built in selftest (instruction tap_test1, code 0100) figure 7 readout of selftest result (after 10240 tck periods) note: after the use of the selftest procedure over the m p interface or the boundary scan interface a hardware reset is necessary before the selftest procedure can be started again over the other interface. 2.3.4 idcode the manufacturer code for mtsxl is according to table 2: v1.2: 0010 0000 0000 0010 0101 0000 1000 001 1
peb 2447 operational description semiconductor group 23 03.97 3 operational description 3.1 initialization procedure for a proper initialization of the mtsxl the following procedure is recommended: first a reset pulse (res) of at least two clk clock periods has to be applied. all registers contain now their reset values. in the next step the connection memories cm0/1 are initialized by the commands cmdr:stp (1:0) = 01 (cm reset) or cmdr:stp (2:0) = 011 / 111 (mtsxl selftest). after having programmed a cm reset command, it takes 4096 clock periods until all tristate control entries in the cm contain the value 1 (tristated). if a selftest command was given, it takes 10 240 clock periods to achieve the same effect. furthermore the register bit star:stok (selftest o.k.) should read 1 in this case, in order to prove that there is no fault on the chip. the selftest command must be given twice: the upper half of data memory (dm0, dm1) is tested when setting cmdr:stp (2:1) = 01, the lower half of dm0, dm1 is tested by setting cmdr:stp (2:1) = 11 (see table 10 ). the activity of the procedures can be monitored in star:pact and an interrupt will indicate their completion. in all cases it is important, that the outputs are tristated by modr:psb = 0. 3.2 operation mode the operation mode of the device is fixed by programming modr:md (1:0) (see table 9 ). 3.3 indirect access registers the connection memories and data memories are accessible through the indirect access registers mach, maal, mrdh, mrdl, mwdh and mwdl. an indirect access is actually started by writing register mach (memory access address/code register high). the code value inherent in this register defines, what action has to be performed. the low byte of the complete access address must be programmed to maal (memory access address register low) before writing to mach. if data are necessary to perform the access (e.g. in write operations), they have to be entered into mwdh (memory write data register high) and mwdl (memory write data register low) before. in read accesses the corresponding registers mrdh (memory read data register high) and mrdl (memory read data register low) contain the required information after the internal read process is completed.
peb 2447 operational description semiconductor group 24 03.97 typical write operation: typical read operation: wr mwdl wr maal wr mwdh wr mach wr maal rd star; star:mac = 0 wr mach rd mrdl rd star; star:mac = 0 rd mrdh 3.4 frame evaluation if the device is in synchronized state (star:pss = 1) and for example the command frame evaluation at fs5 (cmdr = 58 h ) is programmed, the second following rising edge of fs5 is evaluated and creates the following result in register ferh:ferl (see also table 15 ): figure 8 frame evaluation note: the frame evaluation procedure gives (roughly) the number to be programmed in icsr (after inversion of fer0): fev 11..1 give the number of complete clk periods; fev 0 gives the sampling edge (falling / rising). due to the internal delay in the mtsxl the sampling region and therefor the result in fev 11..1 is shifted against clk for a time x which is uncertain between 0 < x < 13 ns. if the rising edge of fs occurs in that uncertain region the value of fer 11..1 might vary + 1 (fer 0 inverted before!).
peb 2447 operational description semiconductor group 25 03.97 3.5 input offset and output offset based on the results of the frame evaluation procedures the input offsets can be adjusted by programming icsr 7..0 corresponding to inputs in 7..0. if data oversampling is used, the values of icsr 7..0 can be adjusted within some limits during operation without producing bit errors: C clockrate = 2 datarate possible adjustment is one half clock period forward or backward. C clockrate = 4 datarate possible adjustment is one clock period backward or two clock periods forward. figure 9 input timing
peb 2447 operational description semiconductor group 26 03.97 figure 10 output timing the output offset is the same for all output lines and is fixed in register ocsr.
peb 2447 operational description semiconductor group 27 03.97 3.6 frame delay figure 11 shows a functional description of the serial input, data memory and serial output. figure 11 internal processing of serial data in mode 0 for example inputs 0 and 8 are both connected to the input shift register. in mode 1 and 3 only input 0 is used and two time slots are always processed together.
peb 2447 operational description semiconductor group 28 03.97 figure 12 internal control signals mode 0 (ocsr = 0) note: o_syn is a control signal for the synchronization of rd and wr access to the data memory and not important for the external functionality. o_syn frequency is f clk / 2. this figure shows that the inputs in0 .. in15 are written into the data memory at the same time whereas in16 .. in31 are written one o_syn period (= 2 clk periods) later. the value of icsr 0..15 shifts the sampling points and the signal ld inp buffer 1 later in time (rightwards), the signals ld inp buffer 2 and wr s memory remain constant. in this example with ocsr = 0 the lower inputs in0 .. in15 are written into data memory before out15 (and out31) is read. with ocsr > 0 all output signals (ld outp buffer and following) including the data (out0..15) on the internal data transfer bus is shifted earlier in time (leftwards). therefor the data is read out of the data memory earlier. due to the internal timing the frame delay is depending on the programmed input / output time slots and ocsr. the internal delay (number of time slots) can be deduced from figure 12 and is shown in table 7 .
peb 2447 operational description semiconductor group 29 03.97 if the offset of output time slot to input time slot is greater or equal to the internal delay due to table 7 the transmission of data is within the same frame (frame delay 0). if the offset is smaller or even negative the transmission is in the next frame (frame delay 1). frame delay 1 also occurs when the programmed connection overrides the frame end (ts63 in mode 0). if the offset is smaller and overrides the frame end at the same time the frame delay is 2. examples: connection in1 ts1 -> out1 ts 5 (offset 4ts) : frame delay 0 (ocsr=0) in1 ts1 -> out1 ts 3 (offset 2ts) : frame delay 1 in1 ts62 -> out31 ts 0 (offset 2ts) : frame delay 1 in1 ts62 -> out1 ts 1 (offset 3ts) : frame delay 2 table 7 time slots delay mode 0 ocs(4:0) in outputs 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31 00 - 15 3333333333333332 16 - 31 3333333333333333 10 - 15 3333333333333333 16 - 31 4333333333333333 20 - 15 4333333333333333 16 - 31 4433333333333333 30 - 15 4433333333333333 16 - 31 4443333333333333 . . maximum delay 4 time slots
peb 2447 operational description semiconductor group 30 03.97 figure 13 internal control signals mode 1/3 (ocsr = 0)
peb 2447 operational description semiconductor group 31 03.97 note: the time slot delays given in table 8 are valid only for even input time slots; for odd input time slots all delays have to be reduced by 1 time slots. table 8 time slot delay mode 1 / 3 (deduced from figure 13 , only input time slots 0, 2, 4,..) ocs(4:0) in outputs 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 0 0 - 7 55555554 16 - 23 55555555 1 0 - 7 55555555 16 - 23 65555555 2 0 - 7 65555555 16 - 23 66555555 3 0 - 7 66555555 16 - 23 66655555 . . maximum delay 6 time slots
peb 2447 detailed register description semiconductor group 32 03.97 4 detailed register description 4.1 register address arrangement reg. name access address a4..0 reset value comment refer to page modr rd/wr 00 h 00 h mode register 33 cmdr wr 01 h 00 h command register 34 star rd 01 h 01 h status register 35 ista rd 02 h 00 h interrupt status register 36 mask wr 02 h 0f h mask register 37 mach rd/wr 04 h 0x h memory access address/code register high 37 maal rd/wr 03 h xx h memory access address register low 38 mrdl rd/wr 05 h xx h memory read data register low 39 mrdh rd/wr 06 h 0x h memory read data register high 39 mwdl rd/wr 07 h xx h memory write data register low 39 mwdh rd/wr 08 h xx h memory write data register high 40 icsr (15:0) rd/wr 10 h .. 1f h 00 h input clock shift register bank 41 oscr rd/wr 0b h 00 h output clock shift register 42 tstr rd/wr 0c h c0 h test register 42 ferl rd 0e h xx h frame evaluation register low 43 ferh rd 0f h xx h frame evaluation register high 43
peb 2447 detailed register description semiconductor group 33 03.97 4.2 mode register (modr) access in demultiplexed m p-interface mode: read/write, address: 00 h reset value: 00 h psb pcm stand by ; a logical 0 switches the pcm interface outputs to high impedance. md1 md0 mode ; these bits define the chip operation mode according to the following table: note: * ) in mode 3 the pcm lines out(n+16) drive the inverted values of lines out(n) or are tristated, if the corresponding pcm line is tristated. bit 7 bit 0 psb00000md1md0 table 9 operation modes operation mode mode bits md1 md0 input # of ports input data rate [mhz] output # of ports output data rate [mhz] mode 0 0 0 32 4.096 32 4.096 mode 1 0 1 16 8.192 16 8.192 mode 3 1 1 16 8.192 16 16 * ) 8.192 8.192
peb 2447 detailed register description semiconductor group 34 03.97 4.3 command register (cmdr) access in demultiplexed m p-interface mode: write, address: 01 h reset value: 00 h (not readable) fsad2..0 frame synchronization signal address 2 to 0; address of the chosen fs signal 5 to 0 to be evaluated by the procedure started by sfe. sfe start frame evaluation ; a one in this bit position starts the frame evaluation procedure. a read operation on register fer will stop an unfinished frame evaluation procedure. stp2..0 start procedure . the following procedures can be activated by these bits: x: dont care note: before activating one of these procedures modr:psb has to be set to 0. during selftest or cm reset the device will ignore the external synchronization pulse and the user has no access to the internal data memory. bit 7 bit 0 0 fsad2 fsad1 fsad0 sfe stp2 stp1 stp0 table 10 stp commands stp2 stp1 stp0 function x x 0 1 x 0 1 1 0 1 1 1 no operation start control memory reset procedure start selftest procedure (1st part) start selftest procedure (2nd part)
peb 2447 detailed register description semiconductor group 35 03.97 4.4 status register (star) access in demultiplexed m p-interface mode: read, address: 01 h reset value: 01 h fsad2..0 frame synchronization signal address : see cmdr. mac memory access active ; an indirect memory access is active, if this bit is 1, all memory access registers must not be written until mac = 0. pact procedure active ; one of the procedures started by the m p (selftest, cm reset or frame evaluation) is active. pss pcm synchronization status 1: the pcm interface is synchronized 0: the pcm interface is not synchronized. (see note in chapter 4.5 ) stok selftest o.k .; after a selftest procedure this bit is set to 1, if no faults are detected. note: this bit is only valid, if no power failure or inappropriate clocking occurred during the test (see ista:ir); this bit is set to 1 by a start selftest command or by hardware reset. bit 7 bit 0 0 fsad2 fsad1 fsad0 mac pact pss stok
peb 2447 detailed register description semiconductor group 36 03.97 4.5 interrupt status register (ista) access in demultiplexed m p-interface mode: read, address: 02 h reset value: 00 h fec frame evaluation completed ; the indirect register fer contains a valid offset and can be read. pc procedure completed ; the procedure started from the command register (cm reset or mtsxl selftest) is finished. ir initialization request . the connection memory has to be programmed due to a loss of data (ir = 1). the ir bit is set after power failure or inappropriate clocking. it can only be retriggered again after a selftest or cm reset procedure. pfi pcm framing interrupt ; this bit being logical 1 indicates the loss or gain of synchronization. synchronization is considered lost by the mtsxl if the sp signal is not repeated within the correct period. synchronization is considered achieved, if two consecutive sp pulses with the correct period have been received. any interrupt will activate the int line if it is not masked. all interrupt bits and the int line are reset when reading ista. note 1: all interrupts and the int line are cleared with reset. note 2: if the sp signal is repeated within a multiple of frame length (e.g. 2 or 4 125 m s) but at correct phase: C the mtsxl works correctly because the internal counters run autonomously and are synchronized within correct phase. C the pfi interrupt does not occur because this situation is internally handled as loss of synchronization and this situation does not change. note 3: during selftest no pfi interrupt will occur. bit 7 bit 0 0000fecpcirpfi
peb 2447 detailed register description semiconductor group 37 03.97 4.6 mask register (mask) access in demultiplexed m p-interface mode: write, address: 02 h reset value: 0f h a logical 1 disables the corresponding interrupt as described in ista from activating the int pin. a masked interrupt (bit set to 1) is stored internally and indicated, when reading ista. it is also reset in this case. 4.7 memory access address/code register high (mach) access in demultiplexed m p-interface mode: read/write, address: 04 h reset value: 0x h a write access (rising edge of wr or cs ) to this register starts an indirect access to a memory location. mac2..0 memory access code values to determine the type of access to/from control and data memory locations. see table 11 for all possible code values. note: a write & read control memory command actually writes a specific cm location and reads the same location in a second access. ma10..8 memory address (most significant) bits 10 to 8; refer to register maal bit 7 bit 0 0000fecpcirpfi bit 7 bit 0 mac2 mac1 mac0 0 0 ma10 ma9 ma8 table 11 memory access codes mac2 mac1 mac0 function max. access time clock periods 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 no operation write control memory write & read control memory read control memory read data memory C 4.5 6.5 4.5 8.5 all other combinations are not allowed
peb 2447 detailed register description semiconductor group 38 03.97 4.8 memory access address register low (maal) access in a demultiplexed m p-interface mode: read/write, address: 03 h reset value: xx h ma7..0 memory address bits 7 to 0; the complete memory address is the concatenation of ma10..0. if the value ma(10:0) is used as a control memory address, each address corresponds to a single output time slot (see table 12 ): note: port(m) means, that this port drives the inverted data values of port (m-8). for the operation read data memory ma10..0 are used as data memory addresses with the same mapping to the input time slots as listed in the above table. bit 7 bit 0 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 table 12 output time slot mapping mode valid for output (ports) 0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 out (31:0) = port (31:0) time slot number port number 1 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 out (7:0) = port (7:0) out (23:16) = port (15:8) time slot number6..1 pn3 ts0 pn2..0 3 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 out (7:0) = port (7:0) = port (15:8) out (23:16) = port (15:8) = port (31:24) time slot number6..1 pn3 ts0 pn2..0
peb 2447 detailed register description semiconductor group 39 03.97 4.9 memory read data register low (mrdl) access in demultiplexed m p-interface mode: read/write, address: 05 h reset value: xx h mrd7..0 memory read data values (bits 7 to 0); see mrdh; 4.10 memory read data register high (mrdh) access in demultiplexed m p-interface mode: read/write, address: 06 h reset value: 0x h mrd11..8 memory read data values (bits 11 to 8); in a read memory access the requested values can be read in these registers after the access time (see table 11 ). an active access cycle, started by a write access to mach, is indicated by register bit star:mac. 4.11 memory write data register low (mwdl) access in demultiplexed m p-interface mode: read/write, address: 07 h reset value: xx h mwd7..0 memory write data values (bits 7 to 0); see mwdh; bit 7 bit 0 mrd7 mrd6 mrd5 mrd4 mrd3 mrd2 mrd1 mrd0 bit 7 bit 0 0 0 0 0 mrd11 mrd10 mrd9 mrd8 bit 7 bit 0 mwd7 mwd6 mwd5 mwd4 mwd3 mwd2 mwd1 mwd0
peb 2447 detailed register description semiconductor group 40 03.97 4.12 memory write data register high (mwdh) access in demultiplexed m p-interface mode: read/write, address: 08 h reset value: xx h mwd11..8 memory write data values (bits 11 to 8); in a write memory access the values to transfer are written to these registers. both registers must not be written during an active access. an active access cycle, started by a write access to mach, is indicated by register bit star:mac. if the values mwd10..0 / mrd10..0 are used as control memory entries, each possible value corresponds to a single input time slot. mwd11 / mrd11 defines, whether the input time slot is switched actively to the pcm output or is switched to high impedance. tsc tristate control value 0: active 1: high impedance; tsc controls whether the output time slot (corresponding to the address of the control memory location) will drive the pcm values or will be tristate. bit 7 bit 0 0 0 0 0 mwd11 mwd10 mwd9 mwd8 table 13 input time slot mapping / programming of output tristate control mode mrd11..0 / mwd11..0 valid for inputs/(ports) 0 d11d10d9d8d7d6 d5 d4 d3 d2d1d0 in (31:0) = port (31:0) tsc time slot number port number 1, 3 d11d10d9d8d7d6 d5 d4 d3 d2d1d0 in (23:16) = port (15:8) in (7:0) = port (7:0) tsc time slot number 6..1 pn3 ts0 pn2..0
peb 2447 detailed register description semiconductor group 41 03.97 4.13 input clock shift register bank icsr (15:0) access in demultiplexed m p-interface mode: read/write, address: 10 h ... 1f h reset value: 00 h adsr add shift register ; a three bit shift register is inserted into the corresponding input(s), resulting in an additional offset for that/those input(s). the sampling point is shifted backwards by 3 clock cycles (see figure 9 ). note: adsr has to be set to 0 in modes 1 and 3. ics4..0 input clock shift; the value of ics4..0 determines the number of clock cycles by which the bit sampling point is shifted forward in all input modes according to figure 9 . rre receive on rising edge ; the pcm data of the corresponding input(s) is sampled with the rising edge of the clock, if this bit is set. these 16 registers determine the individual clock shift of inputs in0 to in15. if more than sixteen inputs are used, two inputs are controlled by one icsr register: icsr0 controls in0, in8 icsr1 in1, in9 icsr2 in2, in10 .. .. icsr7 in7, in15 icsr8 in16, in24 icsr9 in17, in25 icsr10 in18, in16 .. .. icsr15 in23, in31 the values of icsr (15:0) can be adjusted without producing bit errors: C clockrate = 2 datarate possible adjustment is one half clock period forward or backward. C clockrate = 4 datarate possible adjustment is one clock period backward or two clock periods forward. bit 7 bit 0 adrs 0 ics4 ics3 ics2 ics1 ics0 rre
peb 2447 detailed register description semiconductor group 42 03.97 4.14 output clock shift register (oscr) access in demultiplexed m p-interface mode: read/write, address: 0b h reset value: 00 h vn1..0 version number according to the table below: (read only) ocs4..0 output clock shift; these values determine the offset of the output data relative to the sp frame according to figure 10 . xfe transmit on falling edge 0: output data is transmitted with the rising edge of the clock. 1: output data is transmitted with the falling edge of the clock. 4.15 test register (tstr) access in demultiplexed m p-interface mode: read/write, address: 0c h reset value: c0 h stok1..0 selftest ok data memory; these bits are anded for star:stok and can be used for analysis. doa direct output addressing; if this bit is set to 1 the pcm outputs are not switched from the pcm inputs. instead the 8 lsbs programmed to the connection memory are used as data bits, which are shifted out of the corresponding output time slot. the programmed tristate control value keeps its function as in normal operation mode. bit 7 bit 0 vn1 vn0 ocs4 ocs3 ocs2 ocs1 ocs0 xfe table 14 version number vn 1 vn 0 device versions 0 1 a1 (v1.2) bit 7 bit 0 stok1stok000000doa read only
peb 2447 detailed register description semiconductor group 43 03.97 4.16 frame evaluation register low (ferl) access in a demultiplexed m p-interface mode: read, address: 0e h reset value: xx h fev7..0 frame evaluation values (bits 7 to 0); refer to ferh; 4.17 frame evaluation register high (ferh) access in demultiplexed m p-interface mode: read, address: 0f h reset value: xx h fev11..0 frame evaluation values ; after a frame evaluation procedure (interrupt ista:fec) these two registers contain the offset between the sp frame and an evaluated fs0 ... fs5 frame. the evaluation is performed at the second following rising edge of fs after the command cmdr:sfe = 1 was programmed. note: the device must be synchronized to sp (star: pss = 1) in order to generate a correct result in ferl / ferh. note: time constant x is specified to 0 ns < x < 13 ns (see figure 8 ) bit 7 bit 0 fev7 fev6 fev5 fev4 fev3 fev2 fev1 fev0 bit 7 bit 0 0 0 0 0 fev11 fev10 fev9 fev8 table 15 frame evaluation register clk / 1.024 mhz offset value = fev11..1 fev0 fs rising edge between 16 number of clock periods +1 number of clock periods +1 0 1 clock rising edge-x ns and clock falling edge-x ns clock falling edge-x ns and clock rising edge-x ns
peb 2447 electrical characteristics semiconductor group 44 03.97 5 electrical characteristics note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to conditions beyond those indicated in recommended operational conditions of this specification may affect device reliability. table 16 absolute maximum ratings parameter symbol limit values unit ambient temperature under bias t a 0 to 70 c storage temperature t stg C 65 to 150 c supply voltage v dd C 0.3 to 7.0 v input voltage v i C 0.3 to v dd + 0.3 (max 7) v output voltage v o C 0.3 to v dd + 0.3 (max 7) v table 17 dc characteristics ambient temperature under bias range; v dd = 5 v + 5 %, v ss = 0 v parameter symbol limit values unit test condition min. max. l-input voltage v il C 0.4 0.8 v h-input voltage v ih 2.0 v dd + 0.4 v l-output voltage v ol 0.45 v i ol = 2 ma h-output voltage h-output voltage v oh v oh 2.4 v dd C 0.5 v v i oh = C 400 m a i oh = C 100 m a operational power supply current i cc 100 ma v dd = 5 v, inputs at 0 v or v dd , no output loads f clk = 16.384 mhz input leakage current output leakage current i li i lo 1 1 m a m a 0 v < v in < v dd to 0 v 0 v < v out < v dd to 0 v
peb 2447 electrical characteristics semiconductor group 45 03.97 ac characteristics ambient temperature under bias range, v dd = 5 v + 5 %. inputs are driven at 2.4 v for a logical 1 and at 0.4 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and at 0.8 v for a logical 0. the ac testing input/output waveforms are shown below. timing values are guaranteed for capacitive loading of c l = 60 pf on all outputs except pins d(7:0), which are specified for c l = 100 pf. figure 14 i/o waveform for ac tests table 18 capacitances t a = 25 c, v dd = 5 v + 5 %, v ss = 0 v parameter symbol limit values unit min. max. input capacitance c in 5pf output capacitance c out 10 pf i/o capacitance c io 15 pf
peb 2447 electrical characteristics semiconductor group 46 03.97 figure 15 m p read cycle table 19 m p interface timing parameters parameter symbol limit values unit min. max. address setup time to wr , rd t as 10 ns address hold time from wr , rd t ah 0ns rd pulse width t rr 120 ns data output delay from rd cs t rd 100 ns data float from rd t df 25 ns rd control interval t ri 70 ns wr pulse width t ww 60 ns data setup time to wr cs t dw 30 ns data hold time from wr cs t wd 10 ns wr control interval t wi 70 ns int activation delay t id 100 ns int activation/deactivation delay from rd , wr t iid 120 ns
peb 2447 electrical characteristics semiconductor group 47 03.97 figure 16 m p write cycle figure 17 demultiplexed address timing figure 18 interrupt timing
peb 2447 electrical characteristics semiconductor group 48 03.97 table 20 pcm interface characteristics parameter symbol limit values unit condition min. max. clock period clock period low clock period high t cp t cpl t cph 60 27 27 ns ns ns frame setup time frame hold time t fs t fh 7 20 ns ns serial data input setup time serial data input hold time t s t h 9 20 ns ns pcm serial data output delay time t d 50 ns
peb 2447 electrical characteristics semiconductor group 49 03.97 figure 19 ac characteristics at the pcm interface
peb 2447 electrical characteristics semiconductor group 50 03.97 figure 20 ac characteristics at boundary scan interface table 21 boundary scan timing parameter symbol limit values unit condition min. max. test clock period t tcp 160 ns test clock period low t tcpl 80 ns test clock period high t tcph 80 ns tms setup time to tck t mss 30 ns tms hold time from tck t msh 30 ns tdi setup time to tck t dis 30 ns tdi hold time from tck t dih 30 ns tdo delay from tck t dod 60 ns
peb 2447 package outlines semiconductor group 51 03.97 6 package outlines p-mqfp-100-2 (plastic metric quad flat package) gpr05365 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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